Design-Reuse

Designing Using the AMBA (TM) 3 AXI (TM) Protocol -- Easing the Design Challenges and Putting the Verification Task on a Fast Track to Success

The need for higher performance applications is driving the requirement for a new age of on-chip communication infrastructure. Increasing the clock frequency no longer addresses this higher ...
EDN

Synopsys Enhances DesignWare Ethernet IP With Support for IEEE 1588 Specification and ARM AMBA 3 AXI Interface

Synopsys Enhances DesignWare Ethernet IP With Support for IEEE 1588 Specification and ARM AMBA 3 AXI InterfaceSilicon-Proven IP Delivers Precision Clock Synchronization Capabilities and ...
EDN

System Verilog configurable coverage model in an OVM setup – concept of reusability

With the advent of a new era in verification technology based on an advanced HVL like System Verilog, the concept of random stimulus based verification was born, to verify today’s multi‐million gate ...
Electronic Design

Formal Techniques for Protocol Verification: A Case Study On Verifying the ARM ACE Protocol

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.
Semiconductor Engineering

Moving From AMBA ACE to CHI For Coherency

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from the existing AXI protocol to satisfy the cache coherency maintenance demands of SoCs with multi core processors and shared caches in ...
Design-Reuse

Formal Verification IPs: the corner stone for a broader adoption of Formal Verification

Formal verification associated with assertions is a well known approach to functional verification of SoC digital circuits. This technique bears several advantages over dynamic-based solutions, but ...