Semiconductor Engineering

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors

“The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have ...
Electronic Design

Six MOSFETs, Four Pins Create Two-Input Combo NAND/NOR Gate

This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary ...
Design-Reuse

Low Power Universal Gates for Approximate Computing

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...
EDN

Demand for NAND challenges traditional NOR architecture

Though the majority of flash manufacturers supply devices built with the traditional NOR architecture, one of the brighter spots in the flash market is the growing demand for devices built with a NAND ...
Design-Reuse

Efficient logic optimization utilizing complementary behavior of CMOS gates

Any typical digital design style with CMOS uses complementary pairs of p-type and n-type MOSFETs for logic functions implementation. Naturally, CMOS always ought to provide INVERTED outputs like ...
Semiconductor Engineering

What’s After 3D NAND?

Planar NAND flash memory is on its last scaling legs, with 3D NAND set to become the successor to the ubiquitous 2D technology. Samsung Electronics, for one, already has begun shipping the industry’s ...
EDN

Turn a set/reset latch into an astable/monostable multivibrator

This Design Idea describes a simple way to form a reliable astable or monostable multivibrator from a set/reset latch. You may find it useful because it lets you minimize the number of standard ...