EDN

RTL, gate-level tools fill out floor plan flow

SAN MATEO, Calif. — IC floor-planning tool startup InTime Software Inc. will release an RTL floor planner and a gate-level floor planner to complement its architectural-level floor planner at the ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
Semiconductor Engineering

Reusable UPF: Transitioning From RTL To Gate Level Verification

This paper highlights the differences between an RTL UPF and a Gate Level Simulation UPF, and presents a new methodology to write RTL UPF in such a way that minimal changes are required during ...
EDN

Ten-million-gate switched fabric needs better verification

Because Onex is a startup, our design and verification teams require efficient design flows and methodology to be effective. During the design phase of the company's service processor, the Switch ...