Semiconductor Engineering

Automate Memory Test Through A Shared Bus Interface

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point ...
The Next Platform

Mashing Up CXL And OpenCAPI For Shared Disaggregated Memory

The industry is impatient for disaggregated and shared memory for a lot of reasons, and many system architects don’t want to wait until PCI-Express 6.0 or 7.0 transports are in the field and the CXL 3 ...
Semiconductor Engineering

Scalable, Shared-L1-Memory Manycore RISC-V System

A new technical paper titled “MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory” was published by researchers at ETH Zurich and University of Bologna. “Shared L1 memory ...
insideHPC

SGI Installs China's Largest Shared Memory Machine

In order to ensure the success of China’s new polar-orbiting meteorological satellite program, the China National Satellite Meteorological Center [NMSC] has deployed SGI high performance computing and ...